S6: a mezzanine board for ALCT that contains a Spartan-6 FPGA

General description

This board, designed around the Xilinx Spartan-6 FPGA in 2012, serves as a drop-in replacement for the original ALCT mezzanine boards designed ~2002 that used Virtex-E FPGAs. The newer FPGAs offer something like 10x the logic capacity and 2x the speed, making many improvements possible.

Examples of possible improvements (with new firmware) include:

• Internal SEU detection that could prompt for reload from the PROM
• Triple-voting to protect against SEUs
• Additional trigger patterns that can reduce backgrounds from neutrons and low-Pt particles, and give better eta precision for the CSC Track Finder.
• Up to 2x better trigger timing, by making use of both leading and trailing edges of the input signals from AFEBs, i.e. discriminator pulses about 35ns long. (This feature led to 2x better anode timing in offline analysis.)

During Long Shutdown 1, these cards will be installed on ME1/1 and ME4/2 chambers, i.e. on 144 chambers installed in CMS. A total of 160 cards are to be built.

The specific FPGA used is XC6SLX150-3FGG900C.

Useful links and attachments:

• The general description of the ALCT base boards and previous version of mezzanine boards.
• The detailed design document for the Spartan-6 mezzanine card.
• Schematics for the S6 board (8 pages).
• These boards were radiation tested at the UC Davis cyclotron on 15-16 June 2012. They survived the TID tests well up to 3 times the maximum expected for 3000 fb-1 of HL-LHC data, i.e. 30 kRad. (Only a temperature sensor reading was affected at the 30 kRad level.)
• As a part of a US-CMS review of ME1/1 on 20-JUL-2012, there is a full presentation on the S6 board.

Pictures

Top view of the S6 card:

Bottom view of the S6 card: